Many integrated circuits such as single-chip microcomputers require built-in random number generators for purposes such as coding and decoding data. In many cases very large random numbers are required, comprising many digits or bits, which must be assembled from a series of successively generated random numbers. A random number generator should therefore be capable of generating successive random numbers quickly, but it should not require extensive circuitry, since space in an integrated circuit is limited.
One prior-art random number generator comprises an arithmetic unit that repetitively performs certain arithmetic operations, the results of which are kept in a decimal counter. Random numbers are requested by key input by a human operator. When such input occurs, the arithmetic operations are halted and the current counter contents are output as a random number. This random number generator, however, requires extensive counter and arithmetic circuitry, and needs several seconds to generate a random number with a large number of digits.
Another prior-art random number generator uses logic gates and an M-series pseudo-random number generator, for example, to generate a group of clock pulses with differing pulse counts. The clock pulses are counted by a counter, and the counter output is used as a pseudo-random number. This random number generator, however, also requires extensive circuitry and cannot generate random numbers at a rapid rate.
Yet another prior-art random number generator uses a plurality of small-capacity read-only memories from which data are read at independent cycles, and generates long-period pseudo-random numbers by performing arithmetic operations on the data read from the read-only memories. This random number generator, however, is limited in speed by the time needed for performing the arithmetic operations, and requires extensive memory circuitry if it is to generate large random numbers.